VHDLにおけるIF文

count: process(clock)
  begin
    if rising_edge(clock) then
      if switch1 = ’1’ then
        if switch2 = ’1’ then
          output_signal <= ’1’;
        else
          output_signal <= ’0’;
        end if;
      end if;
  end if;
end process;

参考もと

https://cdn.sparkfun.com/datasheets/Dev/FPGA/IntroToSpartanFPGABook.pdf